1. Field of the Invention
The present invention relates to a semiconductor device with embedded memory cells, and more particularly to a semiconductor device with embedded memory cells which can perform tests, a direct access test with a memory tester and a built-in self test with an embedded test circuit, without changes in probing between the semiconductor device and a memory tester.
2. Description of the Related Art
The semiconductor device with embedded memory cells comprises a logic block, a memory block and an embedded test circuit block. In the semiconductor device, the memory tester tests the memory block in the direct access test mode. On the other hand, the logic tester tests the logic block and the embedded test circuit block tests the memory-block in the built-in self test mode, i.e., BIST.
Thus, a conventional semiconductor device with embedded memory cells comprises separate pins: the pins (or pads) used for performing a direct access test on the memory block with a memory tester; and the pins (or pads) used for performing a built-in self test on the logic block and the memory block with a logic tester.
In other words, the direct access test and the built-in self test are used together to test the memory block of the semiconductor device with embedded memory cells.
In order to analyze a defect of the memory block detected in the built-in self test with a logic tester it is necessary to simultaneously perform the direct access test and the built-in self test with a memory tester.
However, there is a problem in the conventional semiconductor device with embedded memory cells in that it is necessary to modify the connection of pins between the memory tester and the semiconductor device when performing the respective tests, because the pins are separately installed for the direct access test mode and the built-in self test mode.
FIG. 1 is a block diagram for illustrating the conventional semiconductor device with embedded memory cells. The semiconductor device 100 comprises a logic block 10, a memory block 20, an embedded test circuit block 30, multiplexers 40, 42, 44, 46, 48 and pads 50, 52, 54, 56, 58, 60, 62.
The functions of respective blocks will be described below. The logic block 10 inputs and outputs data between the memory block 20, thereby performing specific functions that are designed by a designer. The memory block 20 writes and reads data in response to addresses or control signals. The embedded test circuit block 30 responds to BIST control signals sent from outside the device and generates internal addresses, control signals and data signals to write and read data to the memory block 20. The embedded test circuit block 30 also determines whether the read data is identical to the written data and sends the test results about the functional states of the memory block 20 out of the semiconductor device. The pad 50 is used only in the normal operation mode, but not in the test modes. The pad 52 is a control pad to transmit control signals for changing modes between normal operation, the direct access test and the built-in self test. The pad 54 inputs and outputs data with the logic block 10 in the normal operation mode, and transmits addresses to the memory block 20 in the direct access test mode. The pad 56 inputs and outputs data with the logic block 10 in the normal operation mode, and transmits control signals to the memory block 20 in the direct access test mode. The pad 58 inputs and outputs data with the logic block 10 in the normal operation mode, and inputs and outputs data with the memory block 20 in the direct access test mode. The pad 60 inputs and outputs data with the logic block 10 in the normal operation mode, and transmits BIST control signals to the embedded test circuit block 30 in the BIST mode. The pad 62 inputs and outputs data with the logic block 10 o operation mode, and outputs the test result generated from the embedded test circuit block 30 in the BIST mode.
The multiplexer 40 responds to mode control signals to input and output data between the pad 54 and the logic block 10 in the normal operation mode, and to transmit addresses from the pad 54 to the memory block 20 in the direct access test mode. The multiplexer 42 responds to the mode control signals to input and output data between the pad 56 and the logic block 10 in the normal operation mode, and to transmit control signals from the pad 56 to the memory block 20 in the direct access test mode. The multiplexer 44 responds to mode control signals to input and output data between the pad 58 and the logic block 10 in the normal operation mode, and to input and output data between the pad 58 and the memory block 20 in the direct access test mode. The multiplexer 46 responds to mode control signals to input and output data between the pad 60 and the logic block 10 in the normal operation mode, and to transmit BIST control signals from the pad 60 to the embedded test circuit block 30 in the direct access test mode. The multiplexer 48 responds to mode control signals to input and output data between the pad 62 and the logic block 10 in the normal operation mode, and to output the test result generated from the embedded circuit block 30 to the pad 62 in the direct access test mode. The multiplexers 40, 42, 44, 46, 48 are respectively constructed in the structure of a general 2-1 multiplexer.
Reference signs shown in FIG. 1 will be described below. S symbolizes a respective signal in the drawings. S1 is an input and output signal between the pad 50 and the logic block 10. S2 is a mode control signal. S3 is a data input and output signal of the logic block 10. Signals (S8a, b, c, d, e) are those derived from the S3. Signals (S4a, b, c) are input and output signals between the pads 54, 56, 58 and the logic block 10 in the normal operation mode. S4a and S4b are addresses and control signals transmitted from the pads 54, 56 to the memory block 20, and S4c is a test result input and output signal between the pad 58 and the memory block 20. S5a is a BIST control signal transmitted from the pad 60 to the embedded test circuit block 30, and S5b is a test result signal transmitted from the embedded test circuit block 30 to the pad 62. In the built-in self test mode S7a and S7b are respectively related to S5a and S5b. S9 is a signal transmitted between the logic block 10 and the memory block 20, and S10 is a signal transmitted between the memory block 20 and the embedded test circuit block 30. In the drawings these signals do not have one identical bit, but respectively a predetermined bit. Even if each of the pads 50, 52, 54, 56, 58, 60 is respectively shown as one pad, it is not composed of a single pad but grouped by combining the predetermined number of pads with similar functions. The other pads without specific numerals belong to one of those represented in specific reference numerals.
First, the direct access test of the conventional semiconductor device with embedded memory cells will be described with reference to FIG. 1. In the case of the direct access test, a mode control signal is transmitted from the memory tester (not shown) through the pad 52 to the multiplexers 40, 42, 44, 46, 48. The multiplexers 40, 42, 44 output addresses, control signals and data signals to the memory block 20. In the direct access test mode, signals are not input to the pads 50, 60, 62. Therefore, the memory tester writes data through the pad 58 to the memory block 20 and reads the written data to determine whether they are identical to the written data for testing the operational states (normal or defective) of the memory block 20. This direct access test is performed in accordance with the test procedures programmed in the memory tester.
The procedures of the direct access test are briefly described as follows: (1) write data when a write command, addresses and test data are transmitted; (2) read the written data when a read command, addresses and test data are transmitted; and (3) determine whether the read data are identical to the written data for testing the operational state of the memory block 20. This test is performed by repeating the aforementioned procedures of writing and reading data to corresponding addresses, which are increased or decreased.
Next, the built-in self test of the conventional semiconductor device with embedded memory cells will be described with reference to FIG. 1. In the case of the built-in self test, a BIST control signal is sent from the memory tester (not shown) through the pad 52 to the multiplexer 46. In the built-in self test mode, signals are not input to the pads 50, 54, 56, 58, 62. When the BIST control signal is transmitted from the pad 60 through the multiplexer 46 to the embedded test circuit block 30, the built-in self test is performed by transmitting addresses, control signals and data signals from the embedded test circuit block 30 to the memory block 20. The embedded test circuit block 30 increases and decreases addresses, repeats the procedures of writing and reading data to transmit a test result through the multiplexer 48 to the pad 62. The test result is obtained in the embedded test circuit block 30 by determining whether the written data are identical to the read data.
As described above, there is a problem in the conventional semiconductor device with embedded memory cells in that a longer period of time is required for probing respective test modes, especially in switching the test modes because the pads (or pins) are separately installed for respective test modes, the direct access test and the built-in self test.
The present invention is provided to solve the aforementioned problems, and it is a feature of the present invention to provide a semiconductor device with embedded memory cells, the device having a memory tester to perform tests without probing respective test modes especially in switching the test modes between the direct access test and the built-in self test.
In accordance with one feature of the present invention, there is provided a semiconductor device with embedded memory cells, wherein the device comprises a memory block, a logic block for inputting and outputting data with the memory block and performing specific functions and an embedded test circuit block for testing the memory block inside thereof in accordance with the signals input from outside the device. The device comprises: a first signal terminal group for inputting mode control signals from outside to perform normal operation, direct access test and built-in self test; a second signal terminal group for inputting and outputting the data sent from outside to the logic block; a third signal terminal group for transmitting addresses from outside to the memory block in the direct access test mode and for inputting and outputting data with the logic block in the normal operation mode; a fourth signal terminal group for transmitting the mode control signals to the memory block in the direct access test mode, for inputting and outputting data with the logic block in the normal operation mode and for transmitting mode control signals to the embedded circuit block in the built-in self test mode; a fifth signal terminal group for inputting and outputting the test result with the memory block in the direct access test mode, for inputting and outputting data with the logic block in the normal operation mode and for outputting the test result generated from the embedded test circuit block to outside; first selection apparatus for transmitting data between the third signal terminal group and the logic block in the normal operation mode in response to mode control signals and for transmitting addresses from the third signal terminal group to the memory block in the direct access test mode; second selection apparatus for transmitting data between the fourth signal terminal group and the logic block in the normal operation mode in response to mode control signals and for transmitting control signals from the fourth signal terminal group to the memory block in the direct access test mode and for transmitting control signals from the fourth signal terminal group to the embedded test circuit block in the built-in self test mode; and third selection apparatus for transmitting data between the fifth signal terminal group and the logic block in the normal operation mode in response to the mode control signals and for inputting and outputting data between the fifth signal terminal groups and memory block in the direct access test mode and for outputting the test result from the embedded test circuit block through the fifth signal terminal group in the built-in self test mode.
In accordance with another feature of the invention, there is provided a semiconductor device with embedded memory cells having at least three modes, a normal operation, a direct access test and a built-in self test. The device comprises: a logic block for inputting and outputting data from a memory block; a memory block for writing and reading data in response to addresses or control signals; an embedded test circuit block for performing read/write tests on the memory block; at least three multiplexers; a control pad to transmit mode control signals to at least one multiplexer for changing modes between the normal operation, direct access test and built-in self test; a first pad for inputting and outputting data with the logic block in the normal operation mode, and transmitting addresses to the memory block in the direct access test mode; a second pad for inputting and outputting data with the logic block in the normal operation mode, transmitting control signals to the memory block in the direct access test mode, and transmitting BIST control signals to the embedded test circuit block in the built-in self test mode; a third pad for inputting and outputting data with the logic block in the normal operation mode, inputting and outputting data with the memory block in the direct access test mode, and outputting a test result generated from the embedded test circuit block in the built-in self test mode.
In accordance with another feature of the invention, there is provided a semiconductor device with embedded memory cells having three modes of operation: a normal operation, a direct access test and a built-in self test. The device comprises: a logic block; a memory block; an embedded test circuit block; first means for transmitting control signals for changing modes between the normal operation, direct access test and built-in self test; second means for inputting and outputting data with the logic block in the normal operation mode, and transmitting addresses to the memory block in the direct access test mode; third means for inputting and outputting data with the logic block in the normal operation mode, transmitting control signals to the memory block in the direct access test mode, and transmitting BIST control signals to the embedded test circuit block in the built-in self test mode; fourth means for inputting and outputting data with the logic block in the normal operation mode, inputting and outputting data with the memory block in the direct access test mode, and outputting a test result generated from the embedded test circuit block in the built-in self test mode; fifth means for responding to mode control signals and to input and output data between the second means and the logic block in the normal operation mode, and to transmit addresses from the second means to the memory block in the direct access test mode; sixth means for responding to the mode control signals and to input and output data between the third means and the logic block in the normal operation mode, to transmit control signals from the third means to the memory block in the direct access test mode, and to transmit BIST control signals from the third means to the embedded test circuit block in the built-in self test mode; and seventh means for responding to the mode control signals and to input and output data between the fourth means and the logic block in the normal operation mode, to input and output data between the fourth means and the memory block in the direct access test mode, and to output a test result generated from the embedded test circuit block to the fourth means in the built-in self test mode.